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[1503] - posted: 2015-01-22 00:14:31
You're right. I will correct this.

Edit: Updated for next release.

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[1538] - posted: 2015-01-29 14:43:40
Still not supported shifts in which number of bits specified in CL register.
This was for test:
Code:
//;;;;;;;;;;;;
//;  REG32   ;
//;;;;;;;;;;;;
shr eax, cl;
shr ebx, cl;
shr ecx, cl;
shr edx, cl;
shr esi, cl;
shr edi, cl;
shr ebp, cl;
shr esp, cl;

shl eax, cl;
shl ebx, cl;
shl ecx, cl;
shl edx, cl;
shl esi, cl;
shl edi, cl;
shl ebp, cl;
shl esp, cl;

sar eax, cl;
sar ebx, cl;
sar ecx, cl;
sar edx, cl;
sar esi, cl;
sar edi, cl;
sar ebp, cl;
sar esp, cl;

ror eax, cl;
ror ebx, cl;
ror ecx, cl;
ror edx, cl;
ror esi, cl;
ror edi, cl;
ror ebp, cl;
ror esp, cl;

rol eax, cl;
rol ebx, cl;
rol ecx, cl;
rol edx, cl;
rol esi, cl;
rol edi, cl;
rol ebp, cl;
rol esp, cl;

rcr eax, cl;
rcr ebx, cl;
rcr ecx, cl;
rcr edx, cl;
rcr esi, cl;
rcr edi, cl;
rcr ebp, cl;
rcr esp, cl;

rcl eax, cl;
rcl ebx, cl;
rcl ecx, cl;
rcl edx, cl;
rcl esi, cl;
rcl edi, cl;
rcl ebp, cl;
rcl esp, cl;
//;;;;;;;;;;;;
//;  REG16   ;
//;;;;;;;;;;;;
shr ax, cl;
shr bx, cl;
shr cx, cl;
shr dx, cl;
shr si, cl;
shr di, cl;
shr bp, cl;
shr sp, cl;

shl ax, cl;
shl bx, cl;
shl cx, cl;
shl dx, cl;
shl si, cl;
shl di, cl;
shl bp, cl;
shl sp, cl;

sar ax, cl;
sar bx, cl;
sar cx, cl;
sar dx, cl;
sar si, cl;
sar di, cl;
sar bp, cl;
sar sp, cl;

ror ax, cl;
ror bx, cl;
ror cx, cl;
ror dx, cl;
ror si, cl;
ror di, cl;
ror bp, cl;
ror sp, cl;

rol ax, cl;
rol bx, cl;
rol cx, cl;
rol dx, cl;
rol si, cl;
rol di, cl;
rol bp, cl;
rol sp, cl;

rcr ax, cl;
rcr bx, cl;
rcr cx, cl;
rcr dx, cl;
rcr si, cl;
rcr di, cl;
rcr bp, cl;
rcr sp, cl;

rcl ax, cl;
rcl bx, cl;
rcl cx, cl;
rcl dx, cl;
rcl si, cl;
rcl di, cl;
rcl bp, cl;
rcl sp, cl;
//;;;;;;;;;;;;
//;   REG8   ;
//;;;;;;;;;;;;
shr al, cl;
shr bl, cl;
shr cl, cl;
shr dl, cl;

shl al, cl;
shl bl, cl;
shl cl, cl;
shl dl, cl;

sar al, cl;
sar bl, cl;
sar cl, cl;
sar dl, cl;

shr ah, cl;
shr bh, cl;
shr ch, cl;
shr dh, cl;
     
shl ah, cl;
shl bh, cl;
shl ch, cl;
shl dh, cl;
     
sar ah, cl;
sar bh, cl;
sar ch, cl;
sar dh, cl;

ror al, cl;
ror bl, cl;
ror cl, cl;
ror dl, cl;

rol al, cl;
rol bl, cl;
rol cl, cl;
rol dl, cl;

rcr al, cl;
rcr bl, cl;
rcr cl, cl;
rcr dl, cl;

rcl al, cl;
rcl bl, cl;
rcl cl, cl;
rcl dl, cl;

ror ah, cl;
ror bh, cl;
ror ch, cl;
ror dh, cl;

rol ah, cl;
rol bh, cl;
rol ch, cl;
rol dh, cl;

rcr ah, cl;
rcr bh, cl;
rcr ch, cl;
rcr dh, cl;

rcl ah, cl;
rcl bh, cl;
rcl ch, cl;
rcl dh, cl;
//;;;;;;;;;;;;;;;;;;;
//;   dword[REG32]  ;
//;;;;;;;;;;;;;;;;;;;
shr dword[eax], cl;
shr dword[ebx], cl;
shr dword[ecx], cl;
shr dword[edx], cl;
shr dword[esi], cl;
shr dword[edi], cl;
shr dword[ebp], cl;
shr dword[esp], cl;
    
shl dword[eax], cl;
shl dword[ebx], cl;
shl dword[ecx], cl;
shl dword[edx], cl;
shl dword[esi], cl;
shl dword[edi], cl;
shl dword[ebp], cl;
shl dword[esp], cl;
    
sar dword[eax], cl;
sar dword[ebx], cl;
sar dword[ecx], cl;
sar dword[edx], cl;
sar dword[esi], cl;
sar dword[edi], cl;
sar dword[ebp], cl;
sar dword[esp], cl;

ror dword[eax], cl;
ror dword[ebx], cl;
ror dword[ecx], cl;
ror dword[edx], cl;
ror dword[esi], cl;
ror dword[edi], cl;
ror dword[ebp], cl;
ror dword[esp], cl;
    
rol dword[eax], cl;
rol dword[ebx], cl;
rol dword[ecx], cl;
rol dword[edx], cl;
rol dword[esi], cl;
rol dword[edi], cl;
rol dword[ebp], cl;
rol dword[esp], cl;
    
rcr dword[eax], cl;
rcr dword[ebx], cl;
rcr dword[ecx], cl;
rcr dword[edx], cl;
rcr dword[esi], cl;
rcr dword[edi], cl;
rcr dword[ebp], cl;
rcr dword[esp], cl;
    
rcl dword[eax], cl;
rcl dword[ebx], cl;
rcl dword[ecx], cl;
rcl dword[edx], cl;
rcl dword[esi], cl;
rcl dword[edi], cl;
rcl dword[ebp], cl;
rcl dword[esp], cl;
//;;;;;;;;;;;;;;;;;;;
//;   word[REG32]   ;
//;;;;;;;;;;;;;;;;;;;
shr word[eax], cl;
shr word[ebx], cl;
shr word[ecx], cl;
shr word[edx], cl;
shr word[esi], cl;
shr word[edi], cl;
shr word[ebp], cl;
shr word[esp], cl;
    
shl word[eax], cl;
shl word[ebx], cl;
shl word[ecx], cl;
shl word[edx], cl;
shl word[esi], cl;
shl word[edi], cl;
shl word[ebp], cl;
shl word[esp], cl;
    
sar word[eax], cl;
sar word[ebx], cl;
sar word[ecx], cl;
sar word[edx], cl;
sar word[esi], cl;
sar word[edi], cl;
sar word[ebp], cl;
sar word[esp], cl;

ror word[eax], cl;
ror word[ebx], cl;
ror word[ecx], cl;
ror word[edx], cl;
ror word[esi], cl;
ror word[edi], cl;
ror word[ebp], cl;
ror word[esp], cl;
    
rol word[eax], cl;
rol word[ebx], cl;
rol word[ecx], cl;
rol word[edx], cl;
rol word[esi], cl;
rol word[edi], cl;
rol word[ebp], cl;
rol word[esp], cl;
    
rcr word[eax], cl;
rcr word[ebx], cl;
rcr word[ecx], cl;
rcr word[edx], cl;
rcr word[esi], cl;
rcr word[edi], cl;
rcr word[ebp], cl;
rcr word[esp], cl;
    
rcl word[eax], cl;
rcl word[ebx], cl;
rcl word[ecx], cl;
rcl word[edx], cl;
rcl word[esi], cl;
rcl word[edi], cl;
rcl word[ebp], cl;
rcl word[esp], cl;
//;;;;;;;;;;;;;;;;;;;
//;   byte[REG32]   ;
//;;;;;;;;;;;;;;;;;;;
shr byte[eax], cl;
shr byte[ebx], cl;
shr byte[ecx], cl;
shr byte[edx], cl;
shr byte[esi], cl;
shr byte[edi], cl;
shr byte[ebp], cl;
shr byte[esp], cl;
    
shl byte[eax], cl;
shl byte[ebx], cl;
shl byte[ecx], cl;
shl byte[edx], cl;
shl byte[esi], cl;
shl byte[edi], cl;
shl byte[ebp], cl;
shl byte[esp], cl;
    
sar byte[eax], cl;
sar byte[ebx], cl;
sar byte[ecx], cl;
sar byte[edx], cl;
sar byte[esi], cl;
sar byte[edi], cl;
sar byte[ebp], cl;
sar byte[esp], cl;     
     
ror byte[eax], cl;
ror byte[ebx], cl;
ror byte[ecx], cl;
ror byte[edx], cl;
ror byte[esi], cl;
ror byte[edi], cl;
ror byte[ebp], cl;
ror byte[esp], cl;
    
rol byte[eax], cl;
rol byte[ebx], cl;
rol byte[ecx], cl;
rol byte[edx], cl;
rol byte[esi], cl;
rol byte[edi], cl;
rol byte[ebp], cl;
rol byte[esp], cl;

rcr byte[eax], cl;
rcr byte[ebx], cl;
rcr byte[ecx], cl;
rcr byte[edx], cl;
rcr byte[esi], cl;
rcr byte[edi], cl;
rcr byte[ebp], cl;
rcr byte[esp], cl;
    
rcl byte[eax], cl;
rcl byte[ebx], cl;
rcl byte[ecx], cl;
rcl byte[edx], cl;
rcl byte[esi], cl;
rcl byte[edi], cl;
rcl byte[ebp], cl;
rcl byte[esp], cl;
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[1540] - posted: 2015-01-29 16:26:12
Please can you provide further info.... I am not clear as to the issue. Note latest has a small bug which is fixed, I need to take down latest until I get new one out hopefully tonight.

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0CodErr
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[1541] - posted: 2015-01-29 16:30:45
If you try to compile the code above then error occures
Invalid operand(s)
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[1557] - posted: 2015-01-30 22:57:48
Thanks, fixed this for next release.

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[1802] - posted: 2015-02-27 15:06:34
It currently not supported:
Code:
program RAW_IMAGE 'test';

#set bits 32;

dword a, b;

a += b;
a -= b;
a |= b;
a ^= b;
a &= b;
a >> b;
a << b;
a *= b;
a /= b;
but it can be pretty implemented by this way:
Code:
eax = b; add a, eax;              // uses eax
eax = b; sub a, eax;              // uses eax
eax = b; or  a, eax;              // uses eax
eax = b; xor a, eax;              // uses eax
eax = b; and a, eax;              // uses eax
ecx = b; a >> cl;                 // uses ecx
ecx = b; a << cl;                 // uses ecx
eax = a; mul b; a = eax;          // uses eax
eax = a; edx = 0; div b; a = eax; // uses eax, edx
And for signed values need to use 'idiv', 'imul'.
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[1805] - posted: 2015-02-27 15:40:35
I thought about doing this, but I didn't like the idea of eax and edx changing without the programmer understanding this.

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[1807] - posted: 2015-02-27 16:15:41
but I didn't like the idea of eax and edx changing without the programmer understanding this.
Yes, of course, i agree with you. But changes not only registers. The flags also changed. Therefore it should be documented how it works.
Also i suggest to do like with assignment. i.e. use settings of m2m_reg.
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